System-on-Chip Technology Will Deliver More Performance Using Less Power

November 19, 2011

3 Min Read
System-on-Chip Technology Will Deliver More Performance Using Less Power

Designers of next-generation electronic implantable medical devices are coming under increasing pressure to reduce power consumption, prolong battery life, and incorporate components that achieve higher peak performance. Determined to meet these demands, STMicroelectronics (Geneva, Switzerland) is developing a voltage-scalable system-on-chip (SOC) that combines all of these characteristics.

Developed by STMicroelectronics and MIT, a voltage-scalable system-on-chip suitable for electronic implantable medical devices combines low-voltage capacity of 0.6 V, high peak performance, and optimized battery life.

"Since SOCs are already widely used in medical device applications, what's really innovative about this technology is not the SoC itself but its low-voltage functionality," explains Francesco Pappalardo, ultra-low-power platform manager, advanced system technology, at STMicroelectronics. The chip's low-voltage capacity of 0.6 V enables it to exploit the 65-nm CMOS technology not in the on/off area of 1 V but near threshold--the point at which power begins to flow. Because the batteries used in implantable medical devices are not rechargeable, this capability represents a breakthrough by prolonging battery life and reducing the need for repeat surgeries to replace batteries, Pappalardo notes.

Still in development, the company's new low-voltage system-on-chip technology provides high peak performance of 82.5 MHz at the device's maximum voltage of 1.2 V, according to Pappalardo. It also offers high energy efficiency of 10.8 pJ/cycle at 0.6 V while maintaining more than 1.5-MHz clock speeds. "These features will enable the development of new medical implantable applications," Pappalardo adds.

The result of research and development conducted by STMicroelectronics and the Microsystems Technology Laboratories at the Massachusetts Institute of Technology (Cambridge, MA), the low-power SOC offers extensive clock gating and hardware support for 8-, 16-, 20-, 32-bit, and variable-length instructions. It also features separate program and data memories, up to a 32-bit address space, and an optimized programmable interrupt controller unit. In addition, the chip supports up to 64 interrupt sources, includes two 8-kB banks of SRAM for storing instructions and data, and incorporates two miniature instruction and data caches.

"The chip includes many techniques for promoting energy management and long battery life, including clock gating, power gating, and efficient data-path architectures," Pappalardo says. "But the challenge is implementing them in the correct way." For example, the SOC uses direct-mapped, latch-based instruction and data caches at the first level of the hierarchy, further reducing memory-access power consumption. And contributing to the chip's compact, self-contained structure are on-chip ultra-low-power clock generation and analog-to-digital conversion functions. The SOC also features a set of peripherals--such as timers and serial interfaces--that can work at the minimum voltage supply.

STMicroelectronics's system-on-chip technologies are already used in medical device applications, but its new extreme-low-voltage version will be available in the next few years, Pappalardo notes. The chip, he adds, will accommodate all electronic implantable devices--such as pacemakers and implantable cardioverter-defibrillators--that have limited-energy needs, require very high energy efficiency at low frequency levels ranging from 1 to 2 MHz, and can operate at peak performance for very short durations.

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