An MD&DI November 1998 Column
EMI FIELD NOTES
Combining a number of options can reduce electromagnetic interference at the integrated-circuit level.
Medical electronic devices must now often meet requirements for both emissions and immunity in order to be marketed in Europe and domestically. To meet these system level requirements, a designer must consider electromagnetic compatibility (EMC) at many levels of the design, including at the system chassis, printed circuit board, and, increasingly, at the microcontrollers.
Controlling EMI at the integratedcircuit level is becoming more critical. Photo courtesy of Mitel Semiconductor (San Diego).
The EMC characteristics of the integrated circuits (ICs) used in a medical product can have an effect on the test results that may need to be considered. This is especially true for compact devices—such as handheld electronics—or products designed without a metal shielding enclosure.
Reducing board noise and improving immunity to electromagnetic interference (EMI) is usually addressed at the printed circuit board (PCB) and system levels. However, as frequencies increase for ICs, achieving EMC at the microcontroller level is becoming much more important. This article presents a number of recommendations for suppressing EMI at the chip level.
Grounding and Referencing. Using a grid-type or solid ground reference plane can control the loop area of signals in the controllers and reduce overall ground impedance. Using multiple ground pins in the package to tie the internal microcontroller ground to the external PCB ground can also improve grounding.
To reduce electromagnetic noise and improve immunity to electrostatic discharge (ESD) and electrical fast transients (EFTs), a grounding system should be designed to achieve the following goals:
- Provide a low-impedance path for all internal controller signals to return to their sources.
- Minimize the loop area for return current by allowing a return path that is located close to the source signal.
- Provide a low-impedance path for externally generated noise current (such as that induced by ESD) to exit the controller without creating a noise voltage in the ground of the controller.
Ideally, a solid ground reference plane achieves these goals with the lowest possible impedance and shortest possible return paths for all signals. However, a grid-type ground can be effective as long as the total impedance of the grid is low enough.
Even though the metallization in semiconductors is highly resistive compared with that in standard conductors, a grid-type ground can still have fairly low impedance because of the parallel effect provided by multiple ground return paths. Sensitive circuits, such as analog circuits, should be isolated physically from noisy digital circuits so that cross talk is minimal and, therefore, not likely to pose a problem, even though the ground references are connected together in the grid.
To evaluate the ground for overall impedance, the grid can be modeled to represent worst-case impedance (and therefore worst-case noise voltage) by taking the point farthest from the ground pin and calculating the total resistance between the two points as a paralleled dc resistance of all the return paths. Then, the total current demand of all circuits can be assumed to be flowing between these two points.
The resulting voltage drop can be calculated by taking the total current multiplied by the resistance of the worst-case path. As long as the drop is below the lowest noise voltage threshold allowed on the most sensitive circuits, the ground reference grid can be considered to have low-enough impedance to protect sensitive circuits from noisy digital circuits. If the noise voltage calculated by this simple method is greater than the allowable noise on the most sensitive circuits, then the grid should be evaluated further to perform a more detailed cross-talk analysis between the noisy and sensitive circuits.
VCC-to-Ground Decoupling and Power Distribution. VCC represents the low-voltage dc supply to the integrated circuit, such as 5 or 12 V. The VCC-to-ground decoupling should be evenly distributed around the microcontroller to reduce the loop area for noise generated in the VCC lines. Using a grid or solid reference for VCC distribution as well as VCC-to-ground decoupling near the VCC input pins improves power distribution.
VCC-to-ground decoupling is important because the VCC traces can carry common-mode switching transient noise current. The magnitude of the radiated field from this current is directly proportional to the magnitude of the current, I, and the loop area traversed by the current, A. Evenly distributing decoupling capacitance around the layout helps reduce the loop area of the higher- frequency components of the switching transient currents.
Input/Output Pad Filtering. Typically, about 5 pF of input pad capacitance, if any, is used on the input/output (I/O) pads (connected to internal ICs). A resistor-capacitor (R-C) filter at each I/O pad can provide better filtering in the 1–1000-MHz frequency range. Using the maximum capacitance value on each pin and a resistor value of approximately 200 provides the best filtering. The maximum practical capacitance value is typically about 40 pF, but larger or smaller values may be required depending on the space available in the IC. Recent research has shown that increasing R-C filtering on I/O pads is the most effective way to reduce these emissions.1
Filtering of the I/O pads is important both for reducing emissions and for preventing ESD from entering the microcontrollers. All pins, except ground pins, should be filtered; ground pins should be tied directly to the grid-type ground. Filtering helps prevent emissions by providing a high-frequency return path for noise generated inside an IC. This is critical, because if the noise exits the IC, the external traces and wires (on the PCB and in the system) will radiate much more efficiently than does the package itself.
Current microcontroller designs typically incorporate approximately 5 pF of pin-to-ground capacitance on some pins. In the frequency range of interest (from approximately 100 kHz to 1 GHz), this type of filter yields no filtering until about 100 MHz: 2 dB at 100 MHz and 17 dB at 1 GHz. Such a filter may not have enough capacitance to provide substantial immunity because the bulk of the threat energy for ESD and EFTs is below 100 MHz.
By using 40 pF of capacitance (a typical maximum value) and a series resistance of 250 , the filtering can be improved to yield approximately 6 dB at 10 MHz, 10 dB at 30 MHz, 24 dB at 100 MHz, and 43 dB at 1 GHz. A larger capacitance value on inputs provides filtering of even lower frequencies, further improves ESD performance, and reduces emissions emanating from the bond wires and pins of the IC. All pins—except grounds but including VCC—should have this filtering.
Controlling Signal Parameters. The rise and fall times of the signals, especially clock signals, should be controlled to the slowest possible times that will allow the signal to function properly. Further, the rise and fall times should be as symmetric as possible. In the frequency domain, this reduces higher-frequency harmonics of the signals and controls spectral density by reducing even harmonics.
Waveform symmetry is important because it limits the harmonic content in the frequency domain to odd harmonics. In addition, controlling the rise and fall times to the slowest possible value that still allows the signal to function properly ensures that the harmonics fall off as quickly as possible to reduce the possibility of interference. A nice harmonic roll-off can be achieved by controlling the rise and fall times, which reduces the amount of other suppression measures (such as filtering and shielding) needed at higher frequencies.
Clock Distribution. Limiting the lengths of clock runs by using a star distribution and strategically locating the clock's fan-out further reduces EMI at the IC level. Minimizing the number of clock traces that must make long runs can help. The magnitude of the possible emissions is proportional to the length of a run, so reducing that length by a factor of two yields a 6-dB reduction in its ability to radiate at frequencies below its 1/4 wavelength. A fan-out distribution minimizes the number of long clock runs.
Full Planes. Adding metal layers will help distribute power and ground. This is usually considered a costly solution for low-cost plastic-packaged products, but when combined with the other recommendations, it can be effective. Using fully metallized planes yields the lowest possible impedance and minimal loop area. These planes also provide the maximum electric-field containment. This may be most critical for controllers in demanding EMC environments, such as those located close to a sensitive receiver or a relatively high-power source of radio-frequency (RF) energy.
Although additional metal layers dedicated to distributing power and ground are relatively expensive, they are an effective final solution. It is important to remember that the CISPR and FCC limits for radiated emissions, which are the basis for most EMC design, are based on preventing interference at a distance of 3–10 m. The benefits of full ground and power planes are well known for reducing emissions at the system level. At the microcontroller level, the best possible design not only incorporates all of the other recommendations discussed, but also uses additional metal layers for low-impedance power and ground distribution. Sandwiching the signal traces between the metal power and ground layers minimizes all loop areas and contains the fields generated between the layers.
These recommendations are designed to reduce noise and improve immunity at the microcontroller level. However, these solutions alone may not solve EMC problems in every application, because EMC still requires control at the PCB and system levels as well. In fact, in most product designs, PCB- and system-level considerations are the primary areas to focus on to improve EMC. However, as frequencies increase and the size of integrated circuits approaches a scale similar to the wavelengths of interest—and in some cases similar to the product itself—chip-level suppression measures will increase in importance for achieving overall system EMC.
1.Ham S-H, Yun Y-H, Kim S-H, et al., "A Study of Design for Improved EMI in a Chip Level," in Proceedings of the IEEE International Symposium on EMC, Piscataway, NJ, Institute of Electical and Electronics Engineers, p 547, 1998.
Clark Vitek is an EMC staff engineer for CKC Laboratories, Inc., at its Hillsboro, OR, location.